Highly efficient 24-GHz CMOS linear power amplifier with an adaptive bias circuit

Abstract

A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> ) at a 1-dB-gain-compression-power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.