Journal of Instrumentation · 2015 · 19 citations · 9 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksParallel ComputingAccelerator ArchitectureDirect Memory AccessHardware AccelerationNetwork ArchitectureNetwork LayerStream ProcessingChannelsData Stream ProcessingGpu ArchitectureNetwork Interface DesignReal-time Gpu ComputingReal-time ProcessingRemote Direct Memory AccessTransport Layer Offloading
NaNet is a FPGA-based PCIe Network Interface Card (NIC) design with GPUDirect and Remote Direct Memory Access (RDMA) capabilities featuring a configurable and extensible set of network channels. The design currently supports both standard—Gbe (1000BASE-T) and 10GbE (10Base-R)—and custom—34 Gbps APElink and 2.5 Gbps deterministic latency KM3link—channels, but its modularity allows for straightforward inclusion of other link technologies. The GPUDirect feature combined with a transport layer offload module and a data stream processing stage makes NaNet a low-latency NIC suitable for real-time GPU processing. In this paper we describe the NaNet architecture and its performances, exhibiting two of its use cases: the GPU-based low-level trigger for the RICH detector in the NA62 experiment at CERN and the on-/off-shore data transport system for the KM3NeT-IT underwater neutrino telescope.
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