Analysis, Design, Modeling, and Characterization of Low-Loss Scalable On-Chip Transformers

Abstract

A few important design choices for a low-loss scalable on-chip transformer are discussed, the most important one being that the capacitive and inductive couplings should be aligned to minimize insertion loss. The importance of these design choices is illustrated both theoretically as well as experimentally. In particular, for the first time the performance of these on-chip transformers is verified with four-port <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter measurements taken up to 67 GHz. With that, an insertion loss of only 0.6 dB up to 30 GHz is demonstrated. To facilitate the use of these low-loss on-chip transformers in the RF integrated-circuit design flow, a scalable compact equivalent-circuit model suitable for all pre-layout circuit simulations is described, which accurately predicts transformation ratios, transmission efficiencies and balun amplitude and phase imbalances.