Rapid Thermal Annealed Low Pressure Chemical‐Vapor‐Deposited SiO2 as Gate Dielectric in Silicon MOSFET's

Abstract

A device quality silicon gate dielectric technology compatible with low temperature, low cost, and high volume manufacturing techniques has been developed using an appropriate combination of low pressure chemical‐vapor‐deposited silicon dioxide and rapid thermal annealing. Typical deposition was carried out at 420°C in a vertical dome LPCVD reactor, then annealed at 1000°C for 60s. MOS capacitors and MOSFET's were fabricated by this process, and their C‐V and device characteristics presented. Annealing the LPCVD in oxygen was found to lower the oxide fixed charge density, enhance dielectric strength, and achieve excellent interfacial property compared to as‐deposited LPCVD . This property is thought to be due to a thin rapid thermal oxide grown at the Si/LPCVD interface during oxygen anneal and substantiated by high resolution electron micrograph. Structural properties of these LPCVD films were analyzed by AES, XPS, and infrared techniques.