A 200mW 100MHz-to-4GHz 11<sup>th</sup>-order complex analog memory polynomial predistorter for wireless infrastructure RF amplifiers

Abstract

The trend toward heterogeneous networks encompassing legacy high-power base stations (macro-BTS) with lightweight and easy to deploy small cells calls for inexpensive and efficient Power Amplifier (PA) linearizers. Current macro-BTSs relying on Digital Predistortion Techniques (DPD) are too power hungry and costly to be used in small cells. In this paper, we present a fully integrated, 11th-order, 4-memory term, temperature-compensated complex analog polynomial predistorter. It is implemented in 0.18μm CMOS, does not require calibration and offers up to 25dB linearity improvement. Several integrated [1,2] and discrete [3,4] implementations of Analog Predistorters (APD) have been published. This paper reports a complex high-order predistorter integrating the RF and the IF on the same die (RFPD).