A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS

Abstract

Demand for bandwidth in metro networks and data centers has fueled the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, especially for MMF applications, due to the complexity of the channel pulse response and the dynamic nature of the channel impairment. The reach of the backplane channels can also be extended, providing flexibility for system design. Applications such as 10G SFP+ DAC have less channel loss; consequently, a slicer-based binary receiver is a more viable low-power solution. This work describes the AFE of a dual-path receiver that uses both an ADC path and a slicer path for 10Gb/s multi-standard applications in 40nm CMOS.