Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips

TLDR

Lowering supply voltage reduces microprocessor power consumption but makes chips highly sensitive to process variation, causing large core frequency disparities. This paper proposes Booster, a low‑overhead framework that dynamically rebalances performance heterogeneity arising from process variation and application imbalance. Booster employs two very low but distinct voltage rails, dynamically assigning cores via gating circuits, switching frequencies, and an on‑chip governor that manages a boost budget (with two variants—VAR and SYNC—targeting core‑to‑core variation and multithreaded imbalance respectively). Simulated 32‑core tests on PARSEC and SPLASH2 benchmarks demonstrate average performance gains of 11 % for Booster VAR and 23 % for Booster SYNC.

Abstract

Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process variation, which can lead to large differences in the maximum frequency achieved by individual cores. This paper presents Booster, a simple, low-overhead framework for dynamically rebalancing performance heterogeneity caused by process variation and application imbalance. The Booster CMP includes two power supply rails set at two very low but different voltages. Each core can be dynamically assigned to either of the two rails using a gating circuit. This allows cores to quickly switch between two different frequencies. An on-chip governor controls the timing of the switching and the time spent on each rail. The governor manages a "boost budget" that dictates how many cores can be sped up (depending on the power constraints) at any given time. We present two implementations of Booster: Booster VAR, which virtually eliminates the effects of core-to-core frequency variation in near-threshold CMPs, and Booster SYNC, which additionally reduces the effects of imbalance in multithreaded applications. Evaluation using PARSEC and SPLASH2 benchmarks running on a simulated 32-core system shows an average performance improvement of 11% for Booster VAR and 23% for Booster SYNC.