Saturation Current and On-Resistance Correlation during During Repetitive Short-Circuit Conditions on SiC JFET Transistors

Abstract

This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.