Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques

Abstract

A new redundancy technique termed dotted logic is presented. Critical input errors are eliminated by joining together the output of NAND gates and NOR gates. The remaining subcritical errors are corrected by introducing redundant inputs to each logic element. Two different schemes, dotted alternating and dotted identical, are described and compared with existing error-correcting techniques. It is shown that these new methods have several advantages over quadded or triple modular redundancy (TMR) networks. In addition to correcting single faults, dotted schemes are easily extended to cover multiple faults. Methods for initial failure determinations for dotted schemes are proposed. Finally, it is shown that a network consisting of complex function elements can be made more reliable by dotting.