Design and Analysis of a $Ka$-Band Monolithic High-Efficiency Frequency Quadrupler Using GaAs HBT–HEMT Common-Base/Common-Source Balanced Topology

Abstract

A Ka-band monolithic high-efficiency frequency quadrupler using a GaAs heterojunction bipolar transistor and pseudomorphic high electron-mobility transistor technology is presented in this paper. The frequency quadrupler is constructed cascading two frequency doublers. The frequency doubler employs a modified common-base/common-source topology to enhance the second harmonic efficiently. The dc bias condition, harmonic output power, conversion gain, and efficiency for variable configurations are investigated. Two phase-shifter networks are used to reduce phase error and improve the fundamental rejection. Between 23-30 GHz, the proposed frequency quadrupler features a conversion gain of higher than -1 dB with an input power of 4 dBm. The maximum conversion gain is 2.7 dB at 28 GHz with an efficiency of up to 8% and a power-added efficiency of 3.6%. The maximum output 1-dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB) and the saturation output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) are higher than 7 and 8.2 dBm, respectively. The overall chip size is 2×1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .