40-43-gb/s oc-768 16:1 MUX/CMU chipset with SFI-5 compliance

Abstract

We present two copackaged ICs that provide complete OC-768 16:1 multiplexer (MUX) and clock multiplying unit (CMU) functionality. The 17-input 2.5-2.68-Gb/s parallel interface is Serdes Framer Interface Level 5 (SFI-5) compliant while the 40-43-Gb/s output satisfies OC-768 jitter generation specifications with 7 dB of margin. The system architecture and two-chip partitioning are discussed, followed by descriptions of the design challenges including SFI-5 compliance, 40-Gb/s MUX timing, and 20-GHz clock generation. A novel technique for stabilizing timing margins in the final high-speed multiplexer stage using in-phase and quadrature clocks is also presented. This chipset accommodates 11 bits of static skew and 21 bits of dynamic wander at the SFI-5 interface, while generating 125 fs rms of random jitter and 3.1 ps peak-to-peak of deterministic jitter at its 40-43-Gb/s outputs. The measured bit-error ratio is less than 10/sup -15/ for 2/sup 31/-1 PRBS data and is measurement time limited. The two chips occupy 15.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 8.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area. Both are implemented in a 120-GHz f/sub T/ SiGe BiCMOS process.