IEEE Transactions on Industry Applications · 2015 · 12 citations · 14 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsMixed-signal Integrated Circuit DesignPulse-width ModulationAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersDigital Pulse-width ModulationDigital-to-analog ConvertersLinearityPower Consumption
A design of a new hybrid-type digital pulsewidth modulator (DPWM) with a wide frequency range of 1000:1, from 10 kHz to 10 MHz, is presented. The proposed DPWM has the maximum duty-cycle resolution of 11 bits and consumes the power of 17.5 μW at 10 kHz and 2.36 mW at 10 MHz, respectively. The proposed DPWM realizes the upper 5-bit resolution using a programmable digital counter and the lower 6-bit resolution using a current-integrating-type phase interpolator, employing an M2M-ladder current-steering digital-to-analog converter for low power consumption. The operating clock is generated in on-chip using a relaxation oscillator. The prototype integrated circuit fabricated in a 0.25-μm high-voltage complementary metal-oxide-semiconductor demonstrates that the proposed DPWM maintains a good linearity across the entire operating range.
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