IEEE Journal of Solid-State Circuits · 2000 · 210 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignCurrent-voltage CharacteristicsLeakage Power ReductionPower ManagementShort-channel EffectsVoltage ScalingHigh-speed Cmos DesignHigh-speed OperationLow-power Cmos DesignLow-speed OperationLow-voltage Cmos DesignSub-threshold OperationThreshold VoltageThreshold Voltage Control
A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.
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The impact of gate-induced drain leakage current on MOSFET scaling