A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current

Abstract

A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.