Overview of gate linewidth control in the manufacture of CMOS logic chips

Abstract

This paper is an overview of the methods used at the Burlington facility of the IBM Microelectronics Division to improve channel-length tolerance control in the manufacture of CMOS logic chips. We cover aspects of 1) the impact of channel-length control on chip performance, yield, and reliability; 2) our use of an electrical linewidth monitor which permits high-volume, accurate measurements to quantify polysilicon gate linewidth variability and its improvements; and 3) our efforts to reduce photolithographic and etching contributions to the linewidth variability.