Effective buffer insertion of clock tree for high-speed VLSI circuits

TLDR

Clock delay and skew minimization is crucial in high‑speed VLSI design and can be addressed through routing strategies or buffer insertion in the clock tree. This work proposes an effective buffer‑insertion algorithm aimed at reducing clock delay and skew in high‑speed clock layouts. The algorithm employs a novel interconnection delay model that incorporates crossunders and vias, and uses both minimum‑size and cascaded buffers to lower total delay. It runs in linear time (O(n)) and achieves up to 95 % clock‑delay reduction on practical examples.

Abstract

Clock delay and skew minimization is an important problem in design and layout of high speed VLSI circuits. Clock delay and skew can be minimized either by a good routing strategy, or by inserting buffers in the clock tree. In this paper we develop an effective buffer insertion algorithm for high speed clock layout to minimize the clock delay and skew. Our approach is based on a new interconnection delay model, in which several practical factors such as crossunders and vias are considered in the delay calculation; furthermore, both minimum-size buffers and cascaded clock buffers are used to minimize the total clock delay. The algorithm runs in O (n) time, where n is the number of legal buffer positions in the clock tree, and obtains up to 95% clock delay reduction on practical examples.