Wide-Band Inductorless Low-Noise Transconductance Amplifiers With High Large-Signal Linearity

Abstract

Two high-linearity inductorless broadband low-noise transconductance amplifiers (LNTAs) employing noise and distortion cancellation techniques are presented. The core design employs a common-gate input stage and a common-source error-amplifier (EA) stage. Stacked PMOS-NMOS topology enables large-signal operation while the drain current is reused. The high linearity performance is achieved by the derivative superposition of the pMOS and nMOS transistors that reduce the third-order distortion due to second-order interaction between input stage and EA stage. Critical design issues are carefully investigated along with the performance tradeoffs. In the fully differential architecture, the first LNTA covers 0.1-2-GHz bandwidth and achieves a minimum noise figure (NF) of 3 dB, third-order input intercept point (IIP3) of 10 dBm, and a 1-dB compression point of 0 dBm while dissipating 30.2 mW of dc power. The second lower power LNTA with bulk-driven technique achieves a minimum NF of 3.4 dB, IIP3 of 11 dBm, 0.1-3-GHz bandwidth at 16 mW of power consumption. Each LNTA occupies an active area of 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 45-nm CMOS.