Efficient mapping of the H.264 encoding algorithm onto multiprocessor DSPs

Abstract

With the introduction of a variety of novel coding tools in H.264 has come an increase in complexity that few processor architectures can facilitate. Prior coding loops, such as MPEG-2, provided fewer variations and optional capabilities as a part of the standard implementation; and as such they were readily partitioned in an intuitive manner with little deviation. Induced by the need to scale to such high-complexity algorithms, homogenous multiprocessor architectures are becoming more common. H.264 poses with it several new options to the software architect in approaching the issue of partitioning the coding blocks most efficiently across a multiprocessor architecture. In this paper, we address issues that arise from the mapping of H.264 onto Multiprocessor DSP chips. We discuss aspects of algorithm partitioning, reference frame coherency, and synchronization issues. We show flexible methods for mapping the algorithm onto MDSPs which allow scalability over coding tools, resolutions, and computation/bandwidth availability.