Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC

Abstract

A digital-domain calibration is proposed for a split-capacitor DAC of a 0.5 V 11 bit 10 kS/s differential-type SAR ADC. The calibration improves the linearity of ADC, especially INL by +1.59/-1.71 LSB, SFDR by 19.1 dB, and SNDR by 5.0 dB (ENOB by 0.83 bits). It compensates both the mismatch among binary-weighted capacitors and the errors due to parasitic capacitance of bridge-capacitor and LSB bank. No extra calibration DAC is required in this work, because one of the two differential DAC branches is used to measure errors of the other DAC branch. Measurements on the fabricated chip with a 0.13 μm CMOS process show INL +0.78/-0.89 LSB, DNL +0.75/-0.89 LSB, SNDR 61.7 dB (ENOB 9.96 bits), and SFDR 81.8 dB at the Nyquist rate. The power consumption and FoM of analog block are 560 nW and 55 fJ/conversion-step, respectively.