Systolic digit-serial multiplier

Abstract

A new architecture for digit-serial multiplication is presented. The new digit-serial multiplier is the first reported systolic design where the delay in obtaining the least significant digit (i.e. the initial delay) is independent of the number of digits and hence the wordlength. Although the new architecture has a bidirectional data flow, all the cells are used with 100% efficiency. This is achieved by combining, in a novel way, the operation of two basic cells used in the conventional structures. The proposed multiplier is the ideal design to use in DSP structures that have data feedback paths such as IIR filters, because it has localised communications and has the lowest possible latency as well as being modular and regular. The new structure also allows a high level of pipelining to increase the throughput rate. The performance and the effect of pipelining levels on the throughput rate and hardware cost for the new structure is also presented to allow designers to find the best tradeoff between hardware cost and multiplication time.