Publication | Open Access
A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution
48
Citations
9
References
2008
Year
Unknown Venue
EngineeringComputer Architecture128-Pixel RowOn-chip Column-level 10BIntegrated CircuitsImage SensorProgrammable PhotonicsOptical ComputingPhotonic Integrated CircuitPhotonicsElectrical EngineeringComputer EngineeringMicroelectronicsPhotonic DeviceSingle-photon ImagerDigital Circuit DesignSingle-photon Avalanche DiodesOptoelectronicsTdc Bank
We present an array of 128times128 highly miniaturized SPAD (single-photon avalanche diodes) pixels with a bank of 32 time-to-digital converters (TDCs) on chip. A decoder selects a 128-pixel row. Every group of 4 pixels in the row shares a TDC based on an event-driven mechanism. As a result, row-wise parallel acquisition is obtained with a low number of TDCs. Because of the outstanding timing precision of SPADs and an optimized TDC design, a typical resolution of 97 ps is achieved within a range of 100 ns (10 b) at a maximum rate of 10 MS/s per TDC. The TDC bank exhibits a DNL of 0.08LSB and an INL of 1.89LSB.
| Year | Citations | |
|---|---|---|
Page 1
Page 1