The IMD Sweet Spots Varied with Gate Bias Voltages and Input Powers in RF LDMOS Power Amplifiers

Abstract

In this paper, the intermodulation distortion (IMD) sweet spots that are varied with gate bias voltage and input power in RF power amplifiers are predicted with simple mathematical analysis. The analysis is based on the ID-VGS transfer characteristic curve and odd-order two-tone distortion products. The mathematically derived IMD sweet spots have similar behavior with those of measurement applied to 940 MHz LDMOS RF power amplifiers. The approach can be used in predicting optimum gate bias voltage to minimize the 3rd-order intermodulation (IM3).