Asynchronous balanced gates tolerant to interconnect variability

Abstract

Existing methods for gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a lack of design tools make this requirement very difficult to satisfy in practice. We present a novel asynchronous dual-rail gate design which is power balanced, does not require capacitance matching of the data outputs, and is tolerant to process variability on the routed interconnect between gates.