A DC-powered Josephson flip-flop

Abstract

A novel dc-powered flip-flop logic and/or memory element utilizing two Josephson tunneling gates has been designed and tested. Circuit resistances R, critical currents I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> , and fanout inductances L are chosen so that the gates operate individually in the latching current-steering mode. However, the gates G1 and G2 are interconnected in such a way that if, say, G1 is at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V\neq0</tex> and G2 is at V=0, a switching of G2 to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V\neq0</tex> returns G1 to the V=0 state. The fanout current redistribution, which accompanies this switching event, occurs with a time constant of about L/R. Switching back to the initial state is a symmetric process. Tolerances on circuit parameter values for proper operation are reasonably wide.