Sub-word parallelism in digital signal processing

Abstract

We deal with parallelism at the data level. We describe an implementation of the architectural technique called sub-word parallelism (SWP), which increases parallelism at the data-element-level by means of partitioning a processor's data path. The specific implementation we focus on is based on the TigerSHARC DSP architecture, developed at Analog Devices, Inc. As a result of SWP, the same data path and computation units perform more than one computation on an N-element composite word. This composite word consists of more than one adjacent sub-words. SWP is quite common and exists in production versions of most major general-purpose microprocessors. We also present an implementation of an FIR filter in the TigerSHARC using data-level SWP as an example.