Publication | Closed Access
Solid-State Pulse-Height Encoding System with Pileup Reduction for Counting at High Input Rates
39
Citations
4
References
1963
Year
Pileup ReductionHigh Input RatesPileup ConsiderationsEngineeringData ConverterAnalog DesignComputer EngineeringSystems EngineeringDouble RcPulse PowerInstrumentationDigital Circuit DesignSignal ProcessingSelects Undistorted PulsesAnalog-to-digital Converter
The system described selects undistorted pulses and digitizes them for multichannel pulse-height analysis. The system consists of a double RC differentiating linear amplifier, a low jitter gated single-channel analyzer, a linear gate, and an analog-to-digital converter (ADC). The ADC is comprised of a simple discharge-type pulse-height to time converter, gating a temperature compensated 2-Mc astable multivibrator. A temperature change of 25°C results in an over-all gain change of 1%. Baseline shift is minimized by direct coupling. At an input rate of 100 000 pulses/sec the spectrum shifts by less than 1%. Pileup events are rejected by a unique baseline crossing discriminator. The rejection efficiency is about 80%. The apparent pulse width, for pileup considerations, is thereby reduced from 1.5 to 0.25 μsec. The circuits and their performance are discussed.
| Year | Citations | |
|---|---|---|
Page 1
Page 1