Electron-spin-resonance transistors for quantum computing in silicon-germanium heterostructures

TLDR

Spin‑resonance transistors may form the technological basis for quantum information processing. The study designs a transistor that senses and controls a single‑donor electron spin using advanced band‑structure engineering, while addressing manufacturing limitations and scalability for large‑scale quantum computing. Gate bias moves the electron wave function across alloy layers, exploiting g‑factor differences to tune Zeeman energy for single‑qubit operations and adjusting overlap with neighboring qubits for two‑qubit gates. The authors find that silicon‑germanium alloys enable qubit spacings up to 200 nm, compatible with current lithography, while highlighting manufacturing constraints and scalability challenges.

Abstract

We apply the full power of modern electronic band-structure engineering and epitaxial heterostructures to design a transistor that can sense and control a single-donor electron spin. Spin-resonance transistors may form the technological basis for quantum information processing. One- and two-qubit operations are performed by applying a gate bias. The bias electric field pulls the electron wave function away from the dopant ion into layers of different alloy composition. Owing to the variation of the g factor $(\mathrm{Si}:g=1.998,\mathrm{Ge}:g=1.563),$ this displacement changes the spin Zeeman energy, allowing single-qubit operations. By displacing the electron even further, the overlap with neighboring qubits is affected, which allows two-qubit operations. Certain silicon-germanium alloys allow a qubit spacing as large as 200 nm, which is well within the capabilities of current lithographic techniques. We discuss manufacturing limitations and issues regarding scaling up to a large size computer.