A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

Michiel van Elzakker, Ed van Tuijl, Paul Geraedts, Daniël Schinkel, Eric A.M. Klumperink, Bram Nauta

2008 · 186 citations · 5 references

DOIFull text

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Concepts

Abstract

An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. The charge-redistribution DAC can be used in a simple way to make a SAR ADC. The 10b differential ADC uses bootstrapped NMOS devices to sample the differential input voltage onto two identical charge-redistribution DACs. The test chip is fabricated in a 65nm CMOS process. In this ADC, the MSB is set in between the sampling phase and the first comparison, saving energy and time.

References

5