A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

Abstract

A 2.1 Mpixel 120 frame/s CMOS image sensor with column-parallel ΔΣ ADCs is realized in a 0.13 μm CMOS process. Column-parallel ΔΣ ADC architectures improve the conversion speed while reducing the random noise level as well. Inverter-based SC circuits maximize the power efficiency. This sensor achieves a measured noise floor of 1.9e-, while dissipating 180 mW.