Using cache mechanisms to exploit nonrefreshing DRAMs for on-chip memories

Abstract

On-chip memories are becoming an established feature in single-chip microprocessor designs because they significantly improve performance. It is particularly important for single-chip reduced instruction set computer (RISC) microprocessors to include large, high-speed memories, because RISC chips must reduce off-chip memory delays to achieve the shortest possible cycle time. The use of dynamic RAM for all on-chip cache results in all important increased density of local memory for a given scarce chip area, but complicates the processor control due to the inherent requirement for refreshing. By using simple circuit techniques and making a few modifications to cache organization, the refreshing requirement of dynamic RAM can be eliminated. This new cache design approach is described. It makes use of a selective invalidation technique that invalidates only those cache entries that are not fresh. This is accomplished without interrupting the processor execution stream and without degrading the cache performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>