Novel solutions for suppressing parasitic turn-on behaviour on lateral vertical JFETs

Abstract

The SiC (LV-JFET) has several advantages as a switch component in frequency converters. One challenge, when using the component at high switching speed is the coupled unwanted turn-on of the complementary switch, called parasitic turn-on. This paper presents three different novel solutions to suppress parasitic turn-on for a module design on the gate-drive-unit level. Measurements and improvements results on two of the solutions are presented. The paper shows that the losses could be significantly decreased by active current sources and the proposed clamping solution.