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A CMOS 12K gate array with flexible 10Kb memory
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1984
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Unknown Venue
EngineeringVlsi DesignMemory DesignCmos GateEmerging Memory TechnologyComputer ArchitectureIntegrated CircuitsHardware SystemsMulti-channel Memory ArchitectureComputer MemoryHardware SecurityMemory DevicesLogic GatesElectrical EngineeringCmos 12KComputer EngineeringComputer ScienceMicroelectronicsMemory ArchitectureWiring RegionSemiconductor MemoryBeyond Cmos
A 2μm CMOS gate with transistors throughout the wiring region, suitable for implementing both 12,000 logic gates and 10,000 bits of memory will be described. A single array with 16-word×8bits of RAM (access time of 16ns) and a 16-word×10b first in/first-out memory, will also be covered.