A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

Abstract

In this paper, 40 Gb/s SFI-5-compliant TX and RX chips in 65 nm CMOS technology consume 2.8 W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40 GHz VCO, a 40 Gb/s retiming D-FF, and 40 GHz clock-distribution circuits that lead to a low jitter of 0.57 psrms and 3.1 pspp at 40 Gb/s. A 40/20 GHz clock-timing-adjustment circuit based on a phase interpolator is used to ensure wide-range error-free operations (BER < 101Z) at 39.8 to 44.6 Gb/s. A quadruple loop architecture is introduced in the CDR circuit of the RX, resulting in a 38 Gb/s error-free operation (BER < 101Z) at 231-1 PRBS with a low rms jitter of 210 fs in the recovered clock.