Efficient Software Defined Radio Implementations of GNSS Receivers

Abstract

The advent of the Galileo system in Europe and the modernization plans for global positioning system (GPS) are giving a strong impulse to development of global navigation satellite systems (GNSS). The availability of a variety of new signals is boosting the growth of new services and applications. The next generation of receivers will have to deal with signals in different bandwidths with different modulation schemes. In such a context the reconfigurability offered by software defined radio (SDR) technologies, employing programmable hardware like field programmable gate arrays (FPGAs) and digital signal processors (DSPs), can play an important role. The paper presents a case-study of an efficient hardware/software partitioning for the baseband processor and discusses in detail how to meet the real-time constraints. Finally some results concerning the implementation of the proposed architecture on a prototyping board are given.