CLIP

Abstract

We present a novel technique CLIP for optimizing both theheight and width of CMOS cell layouts in the two-dimensional (2-D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width W cell . Then, another model generatesa 2-D layout that has width W cell and requires a minimumnumber of routing tracks. Run times are in seconds for circuitswith up to 16 transistors. For larger circuits, we extend CLIP to ahierarchical method HCLIP that places series-connected transistorscontiguously. This reduces run times by up to three orders ofmagnitude, and still yields optimal results in over 80% of cases.