A multi trench analog+logic protection (M-TRAP) for substrate crosstalk prevention in a 0.25 /spl mu/m smart power platform with 100V high-side capability

Abstract

We have previously reported a 74 V (typical) high-side capable 0.25 /spl mu/m smart power technology with deep trench and a thick p-epi on P++ substrate (V. Parthasarathy et al, IEDM, p.459-462, 2002). A unique trade-off between high-side capability and substrate injection protection in a power IC process was identified and discussed. In this paper, we reveal a key technology enabler on this platform: an isolation structure which utilizes a series of deep trenches with fixed width outside the power device as a physical barrier to redirect electron flow into a more heavily doped region with low lifetime. We have exploited this technique to realize a parasitic collection current of less than 100 nA for an injected NLDMOS negative drain current of 3 A in a distance of less than 30 /spl mu/m without any guard ring biasing scheme. The high side capability of this platform has been upgraded to 100 V (typical) through innovative device and layout design and without any process modification.