Terahertz imaging detectors in a 65-nm CMOS SOI technology

Abstract

Terahertz imaging detectors implemented in a 65-nm CMOS SOI technology are presented. Low-noise square-law power detection is provided by distributed self-mixing in NFET-based passive mixers with optional integrated amplifiers. The pixels of the imaging array are equipped with folded-dipole antennas designed for through-substrate illumination by an integrated silicon lens. With front-side illumination and conductor backing of the chip a maximum non-amplified responsivity (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> ) of 1.1 kV/W and a minimum noise-equivalent power (NEP) of pW/√Hz is achieved. In the intended lens-integrated backside illumination configuration a further 8-dB improvement of Rv and NEP due to the elimination of substrate modes is predicted by EM simulations.