SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications

TLDR

Increasing design complexity widens the gap between ESL design and RTL synthesis, and an efficient ESL synthesis methodology that combines behavioral synthesis and software generation is still missing. This article introduces SystemCoDesigner, a SystemC‑based ESL tool that automatically optimizes hardware/software SoC implementations for multiple objectives. Starting from a SystemC behavioral model, SystemCoDesigner extracts a mathematical model, performs behavioral synthesis, explores the multi‑objective design space with state‑of‑the‑art optimization algorithms, evaluates design points via accurate performance models, and can generate FPGA bitstreams from optimized SoC designs. SystemCoDesigner is the first fully automated ESL synthesis tool that provides correct‑by‑construction hardware/software SoC generation, and a Motion‑JPEG decoder case study demonstrates variants ranging from software‑only to real‑time hardware implementations on a 50 MHz FPGA.

Abstract

With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C++/SystemC-based input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SystemCoDesigner, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SystemCoDesigner automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SystemCoDesigner permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SystemCoDesigner is the first fully automated ESL synthesis tool providing a correct-by-construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA.