A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency

Abstract

The design and implementation of a high-speed voltage-controlled oscillator (VCO) in 65-nm CMOS technology is presented. The proposed VCO oscillates at the secondary resonant pole of its <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> resonator and achieves a frequency enhancement of 84.7% while compared with a conventional cross-coupled VCO. The proposed VCO is also incorporated into a phase-locked loop (PLL) to generate clock signals above 100 GHz. For a 1.2-V supply, the measured tuning range of this VCO is from 103.057 to 104.581 GHz, and the measured phase noise of this VCO is -101.08 dBc/Hz at 10-MHz offset. The locking range of the PLL is from 103.058 to 104.58 GHz, and its measured in-band phase noise is -80.41 dBc/Hz at 1-MHz offset. The measured reference spur level of this PLL is less than -63.8 dBc while consuming 63 mW from a 1.2-V supply.