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High Speed Response in Optoelectronic Gated Thyristor
27
Citations
4
References
1987
Year
Turn-off Delay TimeElectrical EngineeringHigh Speed ResponseEngineeringNanoelectronicsElectronic EngineeringBias Temperature InstabilityApplied PhysicsExcess CarriersMicroelectronicsOptoelectronicsSemiconductor Device
High speed response in a three terminal p n p n double heterostructure optoelectronic gated thyristor is demonstrated. The gate electrode on the active layer is operated to sweep out excess carriers in the active layer. The turn-off delay time has been measured to be 5 ns, which is two orders of magnitude improvement compared with that for the two terminal mode operation. Furthermore, it has been shown that the turn-off delay time cannot be estimated from the conventional 90-10% fall time.
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