A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter

Abstract

This work proposes a non-uniform sampling analog-to-digital converter (ADC) architecture that embeds an alias-free filter in the asynchronous digital domain to relax the requirements of the analog anti-aliasing filter, improve the overall signal dynamic range, and interface directly with synchronous digital circuitry. Both event-driven voltage and time quantizers are used in the conversion process. Furthermore, an analytical model for estimating their quantization noise power is derived, which matches the numerical simulation with less than 4% deviation within the region of interest. A signal to noise ratio (SNR) improvement of 27dB over conventional, uniformly sampled Nyquist ADCs is obtained given the same 10-bit quantizer.