Comparison of the chip area usage of 2-level and 3-level voltage source converter topologies

Abstract

In the low voltage converter range, 3-phase 3-level VSC topologies are not wide spread in industry because of the increased part count and higher costs, although they are more efficient for higher switching frequencies. In this paper an alternative 3-level topology referred to as T-type is presented, which is very high efficient for medium switching frequencies (4-20 kHz). Additionally, it is shown that the total silicon chip area of a 3-level topology can be lower than in a 2-level topology since the losses are distributed over more components leading to only a small increase in the junction temperature. This allows for the design of a chip area and cost optimized 3-level bridge leg module for the mass market.