IEEE Transactions on Computers · 1970 · 250 citations · 13 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemoryStorage SystemsCachingMemory DevicesMemory HierarchyMemory Subsystem DesignAssociative SearchCache ArchitectureCache ManagementCache MemoryCombinational Logic DesignMain Memory OrganizationMemory Array ArchitectureMemory Arrays
Logic‑in‑memory arrays are attractive because their cost scales with pin count rather than gate count, making them essentially memory elements with integrated combinational logic. The paper presents a logic‑in‑memory computer built around a logic‑enhanced cache memory array. The array functions as a high‑speed cache buffer between CPU and main memory, with operations organized into data blocks called sectors that support arithmetic, logical, and associative searches. This architecture makes main memory behave as if it has processing power and near‑cache performance, enabling massively parallel sector operations that promise orders‑of‑magnitude performance gains at modest cost.
If, as presently projected, the cost of microelectronic arrays in the future will tend to reflect the number of pins on the array rather than the number of gates, the logic-in-memory array is an extremely attractive computer component. Such an array is essentially a microelectronic memory with some combinational logic associated with each storage element. A logic-in-memory computer is described that is organized around a logic-enhanced ``cache'' memory array. Used as a cache, a logic-in-memory array performs as a high-speed buffer between a conventional CPU and a conventional memory. The effect on the computer system of the cache and its control mechanism is to make the main memory appear to have all of the processing capabilities and almost the same performance as the cache. Operations within the array are naturally organized as operations on blocks of data called ``sectors.'' Among the operations that can be performed are arithmetic and logical operations on pairs of elements from two sectors, and a variety of associative search operations on a single sector. For such operations, the main memory of the computer appears to the program to be composed of a collection of logic-in-memory arrays, each the size of a sector. Because of the high-speed, highly parallel sector operations, the logic-in-memory computer points to a new direction for achieving orders of magnitude increase in computer performance. Moreover, since the computer is specifically organized for large-scale integration, the increased performance might be obtained for a comparatively small dollar cost.
13
Cellular Logic-in-Memory Arrays
William H. Kautz · IEEE Transactions on Computers · 1969 · 180 citations
Algorithms for Parallel-Search Memories
Adin D. Falkoff · Journal of the ACM · 1962 · 94 citations