Full-chip verification of UDSM designs

Abstract

describes the problems encountered in typical ultra-deep submicron ~S~designs, and the full-chip interconnect verification methodologies needed to successfully identify these problems before tape-out. We first illustrate that UDSM vertilcation must go well beyond simple geometric and circuit comparison checks to address increasingly important issues such as timing, power integrity, signal integrity, and reliability. The key issues of ~drops in the power grid, electromigration in power and signal lines, clock skew, signal coupling and its effect on timing and noise are described. We present real-world examples of such problems and how to find these problems using full-chip verflcation.