Leakage Power Contributor Modeling

Abstract

Low-power or power-aware design is one of the greatest challenges facing the semiconductor industry. The fidelity of low power design is dependent on the accuracy of power modeling across a wide range of PVT values. This paper describes an alternative “power contributor”based approach to cell leakage characterization that exploits inherent separability of power consumption for different portions of a cell. An experimental use of this approach is also presented that demonstrates how the effort to characterize leakage power can be greatly reduced with only a marginal impact on accuracy.