SEU Tolerant Latch Based on Error Detection

Abstract

This paper presents an SEU hardened latch that can mitigate SEU based on an error detection circuit and a multiplexer. During the hold phase, an SEU on an internal node may upset the logic state of the latch. But the error detection circuit can detect this fault and generate fault indication signals via precharge and discharge operations. The fault indication signals control a multiplexer to select a correct output. Therefore, each latch has some error detection and correction capability.