State-of-the-art of topology processors for EMS and PMU applications and their limitations

Abstract

This article provides a review of the current openly available works in the field of topology processing. The most important works in this area are critically scrutinized, and their limitations are identified. The drawbacks are identified and fully discussed, and their effect on the output of the topology processor is investigated. To support the discussion, the IEEE Reliability Test System 1996 is simulated in real-time to show the deficiencies with the current available topology processor that uses PMU data. The real-time simulation is performed using an eMegaSim Opal-RT real-time simulator which is part of the “SmarTS Lab” at KTH Royal Institute of Technology. Finally, possible potential solutions are briefly proposed as a conclusion.