A multi-threaded coarse-grained array processor for wireless baseband

Abstract

Throughput of wireless communication standards ever increases. Computation requirements for systems implementing those standards increase even more. On battery operated devices, next to high performance a low power implementation is also crucial. Reaching this is only possible by utilizing parallelizations at all levels. The ADRES processor is an embedded coarse-grained reconfigurable baseband processor that already could exploit Data Level Parallelism (DLP), Instruction Level Parallelism (ILP) efficiently. In this paper we present extensions to ADRES to also exploit Task Level Parallelism (TLP) efficiently. We show how we reduce the overhead in communication and synchronization between tasks and demonstrate this on a mapping of an 802.11n 300Mbps standard.