Over one million TPCC with a 45nm 6-core Xeon® CPU

Abstract

This paper describes the 6-core Xeonreg 7400 series processor family, code-name Dunnington, designed for a broad range of highly power efficient servers. The processor consists of three dual-core 45nm Core <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> processors and a shared inclusive 16 MB L3 cache (LLC) integrated on a monolithic 503 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die. The system interface is FSB based with the l/Os incorporated into the center of the die. The core-to-FSB connection is replaced with an on-die low-latency uncore interface. The uncore arbitrates among core, LLC, and external bus requests. The processor has 1.9 B transistors and is implemented in 45nm CMOS using high-kappa metal-gate transistors and nine copper interconnect layers. The maximum thermal design power is 130 W.