2007 · 12 citations · 9 references
EngineeringComputer EngineeringComputer ScienceComputer GraphicsHardware-software Co-designLow-power DesignData CompressionHardware AccelerationImage CompressionImage ProcessingLow-power Fpga DesignSource CodingEncoder DesignHigh-speed Cmos DesignHigh-speed Logic DesignVariable SchedulingVideo Compression
This paper presents an HD720p 30 frames per sec H.264 intra encoder operated at 61 MHz with just 72 K gate count. We achieve the low cost and low operating frequency with the highly utilized variable pixel scheduling, and a modified three-step fast algorithm. Thus, the resulted design only needs half of operating frequency and reduces 30% of area cost compared to the previous HD720p intra encoder design.
9
Feature-based intra-prediction mode decision for H.264
Changsung Kim, Hsman-Huei Shih, C.‐C. Jay Kuo · 2005 · 53 citations