Design, simulation and analysis of the low stray inductance bus bar for voltage source inverters

Abstract

Hard-switching technique under the high voltage and high current is one of main trends of high power inverters. Under this switching mode, the stray parameters of the commutating loops, especially the stray inductance of the DC bus bar, have significant influence on the switching process, electromagnetic interference and component stress of the semiconductor switches. It becomes one of the key points for the safe operation of inverters. Based on an actual 55 kW inverter, the design, simulation and analysis for its bus bar is described in this paper. The bus bar model is built with the method of Partial Element Equivalent Circuit (PEEC), and the stray parameters are extracted from PEEC model and applied in the circuit simulation. Compared with the experimental results, the modeling validity is proved, and the simplified modeling process and design principles for complex physical bus bar are presented.